Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs

Reza Hajisheykhi, Ali Ebnenasir, and Sandeep S. Kulkarni


Since SoC (System on Chip) systems are getting more complex everyday, they are subject to different types of faults including timing faults. Timing has a significant importance in SoC systems. However, their fault-affected models are not studied extensively. In this paper, we present a method for modeling and analyzing timing faults in SystemC Transaction Level Modeling (TLM) programs. The proposed method includes three steps, namely timed model extraction, fault modeling and timed model checking. We use UPPAAL timed automata to formally model the SystemC TLM programs and monitor how the models behave in the presence of timing faults. We analyze our method using two case studies. The first one uses loosely-timed coding style, which has a loose dependency between timing and data. The second one utilizes approximately-timed coding style, which has a stronger dependency between timing and data. Also, unlike the previous work, our approach preserve the semantics of transactions and timing concerns.


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