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Time-triggered Runtime Verification of Component-Based Multi-core Systems

Publication Type
Year of Publication
2015
Conference/Journal Name
International Conference on Runtime Verification (RV)
Publisher
Springer
Abstract
Runtime verification is a complementary technique to exhaustive verification and traditional testing, where a monitor inspects the correctness of a system’s behavior at run time with respect to a set of logical properties. In order to tackle non-uniform intervention of monitoring in embedded real-time systems, in time-triggered runtime verification (TTRV), the monitor runs in parallel with the system under inspection and reads the system state at a fixed frequency for property evaluation. Such a monitor ensures bounded overhead and time-predictable intervention in the system execution. In this paper, we characterize and solve the problem of augmenting a component-based system with TTRV, where different components are expected to run on different computing cores with minimum monitoring overhead at run time. In such a system, the mapping of components to the computing cores adds an additional level of complexity to the optimization problem, which is known to be NP-complete in a single component setting. We present an optimization technique that calculates (1) the mapping of components to computing cores, and (2) the monitoring frequency, such that TTRV’s runtime overhead is minimized. Although dealing with runtime overhead of concurrent systems is a challenging problem due to their inherent complex
nature, our experiments show that our optimization technique is robust and reduces the monitoring overhead by 34%, as compared to various near-optimal monitoring patterns of the components at run time.