Office: Room 3436, Engineering Building
Mail address:
Department of Computer Science
Michigan State University
East Lansing, MI 48824
Internet: ldillon (at) cse (dot) msu (dot) edu
Telephone: +1-517-353-4387
Facsimile: +1-517-432-1061
Research interests: Formal methods for specification and validation of concurrent software systems; software engineering; programming languages
CSE 291 Computational
Thinking Lab (CTL), Fall and Spring
42nd ACM/IEEE International Conference on Software Engineering, Seoul, South Korea, 23—29 May 2020
ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering (ESEC/FSE), Sacramento, CA, USA, Nov 8—13, 2020.
Grace Hopper Celebration of Women in Computing
Michigan Affiliate NCWIT Aspiration in Computing Awards
Michigan Celebration of Women in Computing (MICWIC 2019)
COPSE: Understanding how developers maintain concurrent
software
Synchronization Adorned Unified Modeling Language (saUML)
Meridian: An Integrated Toolkit for Developing Interactive
Distributed Applications
Automated Suport for Testing and Debugging of Real-Time
Programs Using Oracles
An Integrated Toolset for Specifying, Testing and Debugging
Complex Software-Intensive Systems
Those papers (below) that are also on the ACM Authorizer list (above) can be downloaded for free using the authorizer links (above). IEEE does not provide an authorizer service (at least not that I am aware of). If you are unable to purchase or download a free copy of any paper listed here, please send email to the L. Dillon (ldillon at msu dot edu).
Dillon, L.K., "Verifying general safety properties of Ada tasking programs," Software Engineering, IEEE Transactions on , vol.16, no.1, pp.51,63, Jan 1990
doi: 10.1109/32.44363
keywords: {Ada;multiprocessing programs;program verification;Ada tasking programs;automating partial correctness proofs;concurrent programs;deadlock;isolation approach;mutual exclusion;safety properties verification;symbolic execution;Computer science;Concurrent computing;Interference;Interleaved codes;Logic;Mechanical factors;Software safety;System recovery},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=44363&isnumber=1685
Huang, Y.; Dillon, L.K.; Stirewalt, R. E K, "Prototyping synchronization policies for existing programs," Program Comprehension, 2009. ICPC '09. IEEE 17th International Conference on , vol., no., pp.289,290, 17-19 May 2009
doi: 10.1109/ICPC.2009.5090062
keywords: {multi-threading;software maintenance;software prototyping;software tools;synchronisation;multi-threading;program evolution;software tool;synchronization policy prototyper;Access protocols;Computer science;Logic;Production facilities;Programming profession;Prototypes;Rendering (computer graphics);Runtime;System recovery;Yarn},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5090062&isnumber=5090011
Dillon, L.K.; Kutty, C.; Moser, L.E.; Melliar-Smith, P.M.; Ramakrishna, Y. S., "Graphical specifications for concurrent software systems," Software Engineering, 1992. International Conference on , vol., no., pp.214,224, 0-0 1992
doi: 10.1109/ICSE.1992.753501
keywords: {Application software;Concurrent computing;Formal specifications;Hardware;Logic;Mechanical factors;Software standards;Software systems;System testing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=753501&isnumber=16236
Avrunin, G.S.; Dillon, L.K.; Wileden, J.C.; Riddle, W.E., "Constrained expressions: Adding analysis capabilities to design methods for concurrent software systems," Software Engineering, IEEE Transactions on , vol.SE-12, no.2, pp.278,292, Feb. 1986
doi: 10.1109/TSE.1986.6312944
keywords: {parallel processing;software engineering;specification languages;analysis capabilities;closed-form description;concurrent software systems;constrained expression formalism;design languages;design methods;design process;semantics;software engineering;specification;system properties;Computer languages;Concurrent computing;Design methodology;Educational institutions;Filtering;Semantics;Software systems;Ada-based design notation;analysis techniques;concurrent software systems;constrained expressions;design method;event-based},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6312944&isnumber=6312933
Fleming, S.D.; Kraemer, E.; Stirewalt, R. E K; Shaohua Xie; Dillon, L.K., "A study of student strategies for the corrective maintenance of concurrent software," Software Engineering, 2008. ICSE '08. ACM/IEEE 30th International Conference on , vol., no., pp.759,768, 10-18 May 2008
doi: 10.1145/1368088.1368195
keywords: {computer science education;concurrency control;fault diagnosis;multi-threading;program diagnostics;software maintenance;training;action protocols;computer science degree programs;concurrent software;concurrent-programming idiom;corrective maintenance;diagnostic executions;fault diagnosis;multithreaded software systems;program comprehension;software engineering curriculums;student strategies;student training;think-aloud protocols;Computer science;Fault diagnosis;Maintenance engineering;Permission;Protocols;Software engineering;Software maintenance;Software performance;Software systems;Unified modeling language;concurrent programming;software maintenance;think-aloud method},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4814190&isnumber=4814110
Avrunin, G.S.; Corbett, J.C.; Dillon, L.K., "Analyzing partially-implemented real-time systems," Software Engineering, IEEE Transactions on , vol.24, no.8, pp.602,614, Aug 1998
doi: 10.1109/32.707696
keywords: {Ada;algebraic specification;multiprocessing programs;processor scheduling;program diagnostics;real-time systems;temporal logic;Ada-implemented components;GIL;graphical interval logic;high-level specifications;hybrid systems;partially specified components;partially-implemented real-time systems analysis;process scheduling;programming language;real-time concurrent systems;real-time temporal logic;regular expressions;run-time overhead;static analysis;Computer Society;Computer languages;Concurrent computing;Error correction;Logic programming;Processor scheduling;Real time systems;Sequential analysis;System testing;Timing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=707696&isnumber=15329
Ramakrishna, Y. S.; Melliar-Smith, P.M.; Moser, L.E.; Dillon, L.K.; Kutty, G., "Really visual temporal reasoning," Real-Time Systems Symposium, 1993., Proceedings. , vol., no., pp.262,273, 1-3 Dec 1993
doi: 10.1109/REAL.1993.393490
keywords: {automata theory;real-time systems;spatial reasoning;temporal logic;temporal reasoning;theorem proving;RTFIL;Real-Time Future Interval Logic;Timed Buchi Automata;automated theorem prover;decidable;decision procedure;dense real-time temporal logic;duration predicates;emptiness problem;graphical proof environment;graphical specification language;interval modalities;railroad crossing example;real-time proofs;real-time stuttering;simple temporal primitives;timing diagrams;visual logic;visual temporal reasoning;Computer science;Documentation;Formal specifications;Gas insulated transmission lines;Logic;Refining;Specification languages;Timing;Vocabulary},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=393490&isnumber=8952
Stirewalt, R. E K; Behrends, R.; Dillon, L.K., "Safe and Reliable Use of Concurrency in Multi-Threaded Shared-Memory Systems," Software Engineering Workshop, 2005. 29th Annual IEEE/NASA , vol., no., pp.201,210, 7-7 April 2005
doi: 10.1109/SEW.2005.39
keywords: {concurrency control;distributed shared memory systems;multi-threading;object-oriented programming;safety-critical software;synchronisation;concurrency computation;deadlock;module interface;multithreaded shared-memory system;object-oriented language;object-oriented programming;software reliability;software safety;synchronization;Computer languages;Computer science;Concurrent computing;Contracts;Object oriented modeling;Reliability engineering;Safety;Software reusability;System recovery;Writing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1521208&isnumber=32541
Fleming, S.D.; Kraemer, E.; Stirewalt, R. E K; Dillon, L.K., "Debugging Concurrent Software: A Study Using Multithreaded Sequence Diagrams," Visual Languages and Human-Centric Computing (VL/HCC), 2010 IEEE Symposium on , vol., no., pp.33,40, 21-25 Sept. 2010
doi: 10.1109/VLHCC.2010.14
keywords: {Unified Modeling Language;concurrency control;multi-threading;program debugging;software metrics;UML sequence diagram;concurrent software debugging;formal metrics;multithreaded sequence diagram;multithreaded software;thread interactions complexity;Complexity theory;Context;Instruction sets;Measurement;Unified modeling language;Visualization;UML sequence diagrams;concurrent software;empirical software engineering},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5635186&isnumber=5635184
Dillon, L.K.; Stirewalt, R. E K, "Inference graphs: a computational structure supporting generation of customizable and correct analysis components," Software Engineering, IEEE Transactions on , vol.29, no.2, pp.133,150, Feb. 2003
doi: 10.1109/TSE.2003.1178052
keywords: {graphs;program diagnostics;program verification;Amalia analyzers;assurance;computational structure;correctness;formal proof obligation;formal semantic models;inference graph;mature proof methods;operational specifications;operationally defined formal notations;Assembly;Computer Society;Computer science;Design engineering;Design methodology;Design optimization;Inspection;Object oriented modeling;Software design;Software engineering},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1178052&isnumber=26465
Stirewalt, R. E K; Dillon, L.K., "A component-based approach to building formal analysis tools," Software Engineering, 2001. ICSE 2001. Proceedings of the 23rd International Conference on , vol., no., pp.167,176, 12-19 May 2001
doi: 10.1109/ICSE.2001.919091
keywords: {formal verification;object-oriented programming;temporal logic;GenVoca;Lotos;automatic generation framework;automatic-verification capability;behavioral subset;component-based approach;domain model;formal analysis tools;lightweight-analysis components;object-oriented design patterns;software-development environment;stand-alone tools;temporal logic;Computer aided software engineering;Computer science;Formal specifications;Logic;Object oriented modeling;Packaging;Software design;Software engineering;Thyristors;Unified modeling language},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=919091&isnumber=19875
Keyes, D.S.; Dillon, L.K.; Moon Jung Chung, "Analysis of a scheduler for a CAD framework," Software Engineering, 1999. Proceedings of the 1999 International Conference on , vol., no., pp.152,161, 22-22 May 1999
keywords: {CAD;data structures;message passing;multi-threading;processor scheduling;program debugging;program verification;CAD framework;Promela model;Spin simulator;Spin verifier;case study;debugging;huge data structures;irrelevant computations;linear scheduler;liveness properties;message passing;multiple execution threads;scheduler analysis;simple model;software system;Algorithm design and analysis;Analytical models;Citation analysis;Data structures;Permission;Power system modeling;Processor scheduling;Scheduling algorithm;Software algorithms;Yarn},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=841004&isnumber=18169
Avrunin, G.S.; Buy, U.A.; Corbett, J.C.; Dillon, L.K.; Wileden, J.C., "Automated analysis of concurrent systems with the constrained expression toolset," Software Engineering, IEEE Transactions on , vol.17, no.11, pp.1204,1222, Nov 1991
doi: 10.1109/32.106975
keywords: {parallel programming;software tools;Ada-like design language;concurrent systems;constrained expression toolset;expression analysis techniques;programming languages;reachable states;source code;system traces;Computer languages;Error correction codes;Frequency;Handicapped aids;Lifting equipment;Navigation;Operating systems;Performance analysis;Process control;Software systems},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=106975&isnumber=3259
Fleming, S.D.; Kraemer, E.; Stirewalt, R. E K; Dillon, L.K.; Shaohua Xie, "Refining existing theories of program comprehension during maintenance for concurrent software," Program Comprehension, 2008. ICPC 2008. The 16th IEEE International Conference on , vol., no., pp.23,32, 10-13 June 2008
doi: 10.1109/ICPC.2008.40
keywords: {concurrent engineering;software maintenance;concurrent software maintenance;initial design;multithreaded software systems;program comprehension;refining existing theories;Cognitive science;Concurrent computing;Design engineering;Interleaved codes;Programming profession;Software maintenance;Software systems},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4556114&isnumber=4556100
Dillon, L.K., "Symbolic execution-based verification of Ada tasking programs," Ada Applications and Environments, 1988., Third International IEEE Conference on , vol., no., pp.3,13, 23-25 May 1988
doi: 10.1109/ADA.1988.4780
keywords: {Ada;parallel programming;program verification;symbol manipulation;Ada tasking programs;automatic generation;concurrent program;correctness proofs;mutual exclusion;safety properties;sequential programs;symbolic execution model;tasking subset;verification conditions;Computer science;Interleaved codes;Logic;Safety;System recovery},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4780&isnumber=265
Fleming, S.D.; Stirewalt, R. E K; Dillon, L.K., "Using Program Families for Maintenance Experiments," Assessment of Contemporary Modularization Techniques, 2007. ICSE Workshops ACoM '07. First International Workshop on , vol., no., pp.9,9, 20-26 May 2007
doi: 10.1109/ACOM.2007.12
keywords: {error handling;graphical user interfaces;multi-threading;software maintenance;modularization techniques;multithreaded GUI browser;network error handling;program families-based approach;software maintenance experiments;Analytical models;Computer aided software engineering;Computer science;Investments;Maintenance;Performance analysis;Software design;Software engineering;Testing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4228631&isnumber=4228621
Stirewalt, R. E K; Dillon, L.K.; Behrends, R., "Using Views to Specify a Synchronization Aspect for Object-Oriented Languages," Software Engineering Workshop, 2006. SEW '06. 30th Annual IEEE/NASA , vol., no., pp.272,281, April 2006
doi: 10.1109/SEW.2006.41
keywords: {formal specification;multi-threading;object-oriented languages;synchronisation;Z specification;integration semantics;integrative benefit development;multithreaded program;object-oriented languages;programming language extensions;self contained partial specification;software maintenance;software reuse;synchronization units model;view-based approaches;Access protocols;Computer languages;Computer science;Design engineering;Logic programming;Object oriented modeling;Programming profession;Software design;System recovery;Yarn},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4090270&isnumber=4090230
Stirewalt, R. E K; Dillon, L.K.; Kraemer, E.T., "The inference validity problem in legal discovery," Software Engineering - Companion Volume, 2009. ICSE-Companion 2009. 31st International Conference on , vol., no., pp.303,306, 16-24 May 2009
doi: 10.1109/ICSE-COMPANION.2009.5071007
keywords: {computer crime;law;program verification;formal method;inference validity problem;legal discovery;requirements validation problem;software engineering;Computer science;Costs;Databases;Information security;Law;Legal factors;Privacy;Programming profession;Software engineering;Software quality},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5071007&isnumber=5070947
Dillon, L.K.; Stirewalt, R. E K, "Lightweight analysis of operational specifications using inference graphs," Software Engineering, 2001. ICSE 2001. Proceedings of the 23rd International Conference on , vol., no., pp.57,67, 12-19 May 2001
doi: 10.1109/ICSE.2001.919081
keywords: {application generators;computer aided software engineering;formal specification;formal verification;graphs;inference mechanisms;subroutines;Amalia framework;LOTOS;automated software generator;behavior simulation;design patterns;formal methods;formal verification;formally defined abstraction;high-level analyses;inference graphs;lightweight components;lightweight specification analysis;model checking;notation semantics;operational description;operational semantics;operational specifications;representations;software testing;specification languages;specification local behavior;step analyzer;top-down specification traversal;Algorithm design and analysis;Analytical models;Automatic test pattern generation;Automatic testing;Computer science;Design engineering;Engines;Packaging;Pattern analysis;Test pattern generators},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=919081&isnumber=19875
Sarna-Starosta, B.; Stirewalt, R. E K; Dillon, L.K., "Contracts and Middleware for Safe SOA Applications," Systems Development in SOA Environments, 2007. SDSOA '07: ICSE Workshops 2007. International Workshop on , vol., no., pp.5,5, 20-26 May 2007
doi: 10.1109/SDSOA.2007.4
keywords: {formal specification;middleware;software architecture;formal method;middleware;safe service-oriented architecture;Connectors;Containers;Contracts;Degradation;Middleware;Protocols;Quality of service;Safety;Semiconductor optical amplifiers;Service oriented architecture},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4273293&isnumber=4273286
Avrunin, G.S.; Corbett, J.C.; Dillon, L.K., "Analyzing Partially-Implemented Real-Time Systems," Software Engineering, 1997., Proceedings of the 1997 International Conference on , vol., no., pp.228,238, 17-23 May 1997
doi: 10.1109/ICSE.1997.610259
keywords: {Real-time, concurrency, static analysis, Ada, temporal logic, hybrid systems, Graphical Interval Logic;Computer science;Concurrent computing;Electronic equipment testing;Error correction;Logic;Permission;Real time systems;Statistical analysis;System testing;Timing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=610259&isnumber=13372
Avrunin, G.S.; Corbett, J.C.; Dillon, L.K.; Wileden, J.C., "Automated derivation of time bounds in uniprocessor concurrent systems," Software Engineering, IEEE Transactions on , vol.20, no.9, pp.708,719, Sep 1994
doi: 10.1109/32.317429
keywords: {concurrency control;integer programming;real-time systems;scheduling;systems analysis;arbitrary scheduling;complex real-time systems;concurrent software system;concurrent systems;constrained expression toolset;finite state systems;integer programming methods;linear inequalities;lower bounds;single processor;time bound derivation;timing analysis;timing properties;uniprocessor concurrent systems;upper bounds;very large state spaces;Lifting equipment;Linear programming;Optimal scheduling;Processor scheduling;Real time systems;Runtime;Scheduling algorithm;Software systems;State-space methods;Timing},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=317429&isnumber=7648
Kutty, G.; Dillon, L.K.; Moser, L.E.; Melliar-Smith, P.M.; Ramakrishna, Y. S., "Visual tools for temporal reasoning," Visual Languages, 1993., Proceedings 1993 IEEE Symposium on , vol., no., pp.152,159, 24-27 Aug 1993
doi: 10.1109/VL.1993.269591
keywords: {formal specification;parallel programming;software tools;temporal logic;GIL toolkit;Graphical Interval Logic;concurrent systems;specifications;temporal reasoning;visual interface;visual temporal logic;Computer science;Formal specifications;Gas insulated transmission lines;Hardware;Logic design;Prototypes;Signal design;Software design;Timing;User interfaces},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=269591&isnumber=6709