CSE 822 - Reading List
Spring 2001
Textbook Ch1, Ch2, Ch5.1, and Ch5.2.
Parallelization
- William Blume, Ramon Doallo, Rudolf Eigenmann, John Grout, Jay Hoeflinger,
Thomas Lawrence, Jaejin Lee, David Padua, Yunheung Paek, Bill Pottenger,
Lawrence Rauchwerger, and Peng Tu. "Parallel Programming with Polaris".
IEEE Computer, 29(12):78-82, December 1996. (Eric Warmbier)
- David A. Padua and Michael J. Wolfe. "Advanced Compiler Optimizations For
Supercomputers". Communications of the ACM, 29(12), December, 1986.
- Hall, Mary, et. al. Maximizing Multiprocessor Performance with the SUIF
Compiler. IEEE Computer, 29(12), December 1996.
(Eric Warmbier)
Memory consistency models
- Lazy Release Consistency for Software Distributed Shared Memory,
with A.L. Cox and P. Keleher, W. Zwaenepoel, Proceedings of the Nineteenth
International Symposium on Computer Architecture, pp. 13-21, May 1992.
(ps)
(Anthony Broomes)
- CAPSL Technical Memo 16: Location Consistency --
a new Memory Model and Cache Consistency Protocol,
G. Gao and V. Sarkar, Feb 1998
(ps)
(Anthony Broomes)
- Commit-Reconcile and Fences (CRF): A New Memory Model for Architects
and Compiler Writers, X. Shen, Arvind, and L. Rudolph,
International Symposium on Computer Architecture, May 1999.
(ps)
-
Hiding Relaxed Memory Consistency with Compilers,
J. Lee and D. Padua.
In Proceedings of The IEEE International Conference on Parallel
Architectures and Compilation Techniques, October 2000.
( pdf )
Processors-in-Memory Architecture
- Baring it all to Software: Raw Machines,
E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim,
M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal.
IEEE Computer, September 1997, pp. 86-93.
(
pdf)
(Chiping Tang)
- Scalable Processors in the Billion Transistor Era: IRAM",
IEEE Computer September 1997.
(pdf)
(Snehal Pithadia)
-
Automatically Mapping Code in an Intelligent Memory Architecture,
J.Lee, Y. Solihin, and J.Torrellas,
Proceedings of the 7th International Symposium on High Performance
Computer Architecture , Jan. 2001.
(pdf)
(Snehal Pithadia)
Low power
- Watch: A Framwork for Architectural-Level Power Analysis and Optimizations,
David Brooks, Vivek Tiwari, and Margaret Martonosi,
27th International Symposium on Computer Architecture, Jun. 2000.
(pdf)
(Brian Foulds)
- A Unified Energy Framework with Integrated Hardware-Software Optimizations",
N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye,
27th International Symposium on Computer Architecture, Jun. 2000.
(Brian Foulds)
- Compilation Techniques for Low Energy: An Overview",
V. Tiwari, S. Malik, and A. Wolfe, Proceedings of the 1994 IEEE
Symposium on Low Power Electronics, Oct. 1994.
(ps)
(Abhishek Mehta)
- The Technology Behind Crusoe Processors, Transmeta corp., 2000.
(pdf)
(Abhishek Mehta)
- Dynamically Managing Processor Temperature and Power, E. Rohou and M. Smith,
2nd Workshop on Feedback-Directed Optimization, Nov. 1999.
(ps)
Feedback directed compilation
Misc.
- A Scalable Approach to Thread-Level Speculation. J. Steffan,
C. Colohan, A. Zhai, and T. Mowry, Proceedings of the 27th International
Symposium on Computer Architecture, Jun. 2000.
(ps)
(Chiping Tang)
- Selective Value Prediction. B. Calder, G. Reinman, and D. Tullsen,
Proceedings of the 26th International
Symposium on Computer Architecture, May. 1999.
(ps)
(Nimesh P Ambeskar)
- Multiscalar Processors. G. S. Sohi, S. Breach, and T. N. Vijaykumar,
Proceedings of the 22th International Symposium on Computer Architecture, June,
1995. (
ps)
(Nimesh P Ambeskar)
-
In Search of Speculative Thread-Level Parallelism.
J. Oplinger, D. Heine, and M. Lam.
In Proceedings of The IEEE International Conference on Parallel
Architectures and Compilation Techniques, October 1999.
( ps)
(H.D.K. Moonesinghe)
- Simultaneous Multithreading: Maximizing On-Chip Parallelism,
D. Tullsen, S. Eggers, and H. Levy,
Proceedings of the 22nd International
Symposium on Computer Architecture, May. 1995.
(ps)
(H.D.K. Moonesinghe)
-
Adaptive Optimization in the Jalapeno JVM: The Controller's Analytical
Model.
M. Arnold, S. Fink, D. Grove, M. Hind, and P. Sweeney. In FDDO-3
(Xing Fang)
-
Exploiting Method-Level Parallelism in Single-Threaded Java Programs.
M. Chen and K. Olukotun,
Proceedings of the International Conference on Parallel Architectures
and Compilation Techniques, Paris, France, October 1998.
(ps)
(Xing Fang)
-
The 27th Annual International Symposium on Computer Architecture
-
The 7th International Symposium on High Performance Computer Architecture
-
The 33rd International Symposium on Microarchitecture