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March 22nd, Brian Foulds
Watch: A Framwork for Architectural-Level Power Analysis and Optimizations, David Brooks, Vivek Tiwari, and Margaret Martonosi, 27th International Symposium on Computer Architecture, Jun. 2000. (pdf) |
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March 22nd, Eric Warmbier
William Blume, Ramon Doallo, Rudolf Eigenmann, John Grout, Jay Hoeflinger, Thomas Lawrence, Jaejin Lee, David Padua, Yunheung Paek, Bill Pottenger, Lawrence Rauchwerger, and Peng Tu. "Parallel Programming with Polaris". IEEE Computer, 29(12):78-82, December 1996. |
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March 27th, Xing Fang
Adaptive Optimization in the Jalapeno JVM: The Controller's Analytical Model. M. Arnold, S. Fink, D. Grove, M. Hind, and P. Sweeney. In FDDO-3. |
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March 27th, Anthony Broomes
Lazy Release Consistency for Software Distributed Shared Memory, with A.L. Cox and P. Keleher, W. Zwaenepoel, Proceedings of the Nineteenth International Symposium on Computer Architecture, pp. 13-21, May 1992. (ps) |
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March 29th, Brian Foulds
A Unified Energy Framework with Integrated Hardware-Software Optimizations", N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye, 27th International Symposium on Computer Architecture, Jun. 2000. |
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March 29th, Chiping Tang Baring it all to Software: Raw Machines, E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. IEEE Computer, September 1997, pp. 86-93. ( pdf) |
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April 3rd, Xing Fang
Exploiting Method-Level Parallelism in Single-Threaded Java Programs. M. Chen and K. Olukotun, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 1998.( ps) |
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April 3rd, Anthony Broomes
CAPSL Technical Memo 16: Location Consistency -- a new Memory Model and Cache Consistency Protocol, G. Gao and V. Sarkar, Feb 1998 (ps) |
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April 5th, Abhishek Mehta
Instruction Level Power Analysis and Optimization of Software. V. Tiwari, S. Malik, A. Wolfe, and T.C. Lee. Journal of VLSI Signal Processing Systems, Vol. 13, No. 2, August 1996. (ps) |
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April 5th, Chiping Tang
A Scalable Approach to Thread-Level Speculation. J. Steffan, C. Colohan, A. Zhai, and T. Mowry, Proceedings of the 27th International Symposium on Computer Architecture, Jun. 2000. (ps) |
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April 10th, Abhishek Mehta
The Technology Behind Crusoe Processors, Transmeta corp., 2000. (pdf) |
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April 10th, Snehal Pithadia
Scalable Processors in the Billion Transistor Era: IRAM", IEEE Computer September 1997. (pdf) |
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April 12th, Eric Warmbier
M. Hall, et. al. Maximizing Multiprocessor Performance with the SUIF Compiler. IEEE Computer, 29(12), December 1996. |
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April 12th, Nimesh Ambeskar
Selective Value Prediction. B. Calder, G. Reinman, and D. Tullsen, Proceedings of the 26th International Symposium on Computer Architecture, May. 1999. (ps) |
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April 17th, H.D.K. Moonesinghe
In Search of Speculative Thread-Level Parallelism. J. Oplinger, D. Heine, and M. Lam. In Proceedings of The IEEE International Conference on Parallel Architectures and Compilation Techniques, October 1999. ( ps) |
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April 17th, Snehal Pithadia
Automatically Mapping Code in an Intelligent Memory Architecture, J.Lee, Y. Solihin, and J.Torrellas, Proceedings of the 7th International Symposium on High Performance Computer Architecture , Jan. 2001. (pdf) |
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April 19th, H.D.K. Moonesinghe
Simultaneous Multithreading: Maximizing On-Chip Parallelism, D. Tullsen, S. Eggers, and H. Levy, Proceedings of the 22nd International Symposium on Computer Architecture, May. 1995. (ps) |
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April 19th, Nimesh Ambeskar
Multiscalar Processors. G. S. Sohi, S. Breach, and T. N. Vijaykumar, Proceedings of the 22th International Symposium on Computer Architecture, June, 1995. ( ps) |