Exam 1 100 Points Spring 2011 Name __________________ 1.(5 pt) Given the attached diagram Figure 4.51 In the middle of the diagram is an Adder with one input from a unit labeled "Shift Left 2". Which instruction uses those units? A. JR B. JALR C. J D. JAL E. None of the above. 2.(5 pt) Given the attached diagram Figure 4.51 In the middle of the diagram is an Adder with one input from a unit labeled "Shift Left 2". Why "Shift Left 2"? A. Instructions are word aligned. B. Allows Multiply-Accumulate. C. "Return" returns to the instruction that is 4 past the current PC. D. Jumps can only jump to every 4th instruction. E. None of the above. 3.(5 pt) Given the attached diagram Figure 4.51 In the middle of the diagram is an Adder with one input from a unit labeled "Shift Left 2". The input wire to the unit labeled "Shift Left 2" also sends 6 bits to the unit labeled "ALU Control". Which statement is true? A. The input to the unit labeled "Shift Left 2" is 32 bits wide. B. The input to the unit labeled "Shift Left 2" is 30 bits wide. C. The input to the unit labeled "Shift Left 2" is 26 bits wide. D. The input to the unit labeled "Shift Left 2" is 16 bits wide. E. None of the above. 4.(5 pt) Given the attached diagram Figure 4.51 At the bottom of the ID/EX pipeline register two lines come in labeled "Instruction[20-16]" and "Instruction[15-11]" that feed out into a Mux whose control line is labeled "RegDst". Which statement is true? A. The Mux selects destination register between logical and arithmetic instructions. B. The Mux selects result values between logical and arithmetic instructions. C. The Mux selects destination register between R-format and I-format instruction. D. The Mux selects result values between R-format and I-format instruction. E. None of the above. 5. (5 pt) A processor has three classes of instructions, for which the CPI values are known. There are two different sequences of instructions which accomplish the same task, as shown in the table below. Class CPI Sequence X ----- --- ---------- A 1 2 from A B 3 4 from B C 5 2 from C What is the average CPI for Sequence X? A) 2.4 B) 2.6 C) 2.8 D) 3.0 E) None of the above. ############## # Figure 1 # ############## The following sequence of instructions is being processed by a MIPS-like microprocessor whose pipelined datapath is shown in Figure 4.51. ori $2, $0, 0x3200 addi $3, $0, 0x6700 sub $4, $3, $2 # *** Line 1 *** sw $5, 20 ($4) # *** Line 2 *** lw $6, 80 ($4) # *** Line 3 *** add $7, $5, $6 # *** Line 4 *** 6 (5pt) Consider the information in Figure 1 and the instruction "Line 1". From which pipeline register will each of the two operands be routed to the ALU? A) $3: ID/EX $2: ID/EX B) $3: EX/MEM $2: MEM/WB C) $3: MEM/WB $2: MEM/WB D) $3: MEM/WB $2: ID/EX E) None of the above. 7 (5pt) Consider the information in Figure 1 and the instruction "Line 2". From which pipeline register will each of the two operands be routed to the ALU? A) $4: ID/EX 20: ID/EX B) $4: EX/MEM 20: MEM/WB C) $4: MEM/WB 20: MEM/WB D) $4: EX/MEM 20: ID/EX E) None of the above. 8 (5pt) Consider the information in Figure 1 and the instruction "Line 3". From which pipeline register will each of the two operands be routed to the ALU? A) $4: ID/EX 80: ID/EX B) $4: EX/MEM 80: MEM/WB C) $4: MEM/WB 80: MEM/WB D) $4: MEM/WB 80: ID/EX E) None of the above. 9 (5pt) Consider the information in Figure 1 and the instruction "Line 4". From which pipeline register will each of the two operands be routed to the ALU? A) $5: ID/EX $6: ID/EX B) $5: EX/MEM $6: MEM/WB C) $5: MEM/WB $6: MEM/WB D) $5: MEM/WB $6: ID/EX E) None of the above. 10. (11 pt) ARM a. (6 pt) Describe how the ARM and MIPS ISA are similar and how they are different. b. (5 pt) ARM dominates the embedded market. Why? 11.(21 pt) MIPS ISA a. Jump addressing i. Describe how target addresses are calculated in Jump (J and JAL) instructions. ii. Also, explain why the transformations (arithmetic) are a reasonable way to calculate jump addresses. iii. Finally, why are no registers used to calculate the jump address? b. The LW and SW instructions use base addressing (base + offset). i. Describe how an address is calculated in LW and SW. ii. What type of data structure (software) is this "base + offset" designed for? iii. The SW instruction reads two registers, but LW reads only one. Why? 12.(19 pt) Arithmetic a.(6 pt) Given twos-complement binary values x = 00011 and y = 11011 illustrate how x-y is calculated. b.(13 pt) Division i. Draw a diagram of the division hardware. ii. State the division algorithm for that hardware. iii. Using the algorithm divide 101 by 010 13. (18 pt) Figure 4.74 shows an out-of-order, speculative processor, the AMD Opteron X4. a. (6 pt) What is meant by a "speculative" processor? a. (12 pt) Refering to Figure 4.74, decribe how an out-of-order, speculative processor works. Focus on the role of the Commit Unit. Remember to include how branches are handled in the Commit Unit. Include in your answer the role of the sequence of instructions that enter the processor.