<1 north:~/Examples >cat example31.s /****************************************************************************** Example #31 -- SPARC floating point operations ******************************************************************************/ .global main .section ".text" .align 4 main: save %sp, -112, %sp set one, %l0 ! Put address of 1.0 into %l0 set ten, %l1 ! Put address of 10.0 into %l1 set zero, %l2 ! Put address of 0.0 into %l2 ldd [%l0], %f24 ! Constant (%f24/25) <== 1.0 ldd [%l1], %f26 ! Constant (%f26/27) <== 10.0 ldd [%l2], %f16 ! Total (%f16/17) <== 0.0 fmovs %f24, %f18 ! Value (%f18/19) <== 1.0 fmovs %f25, %f19 loop: fcmpd %f18, %f26 ! Compare Value to 10.0 nop fbg endloop ! If greater than or equal to 10.0, exit nop faddd %f16, %f18, %f16 ! Add Value to Total faddd %f18, %f24, %f18 ! Add 1.0 to Value ba loop nop endloop: call iu_registers ! Display contents of IU registers nop call fpu_registers ! Display contents of FPU registers nop call dp_registers ! Display FPU registers (as dp values) nop std %f16, [%sp+96] ! Transfer Total to memory, then back ld [%sp+100], %o2 ! into IU registers (for printf) ld [%sp+96], %o1 set fmt, %o0 call printf nop call fpu_registers ! Display contents of FPU registers nop ret restore .align 8 one: .double 0r1.0 ten: .double 0r10.0 zero: .double 0r0.0 fmt: .asciz "\nTotal: %6.2f\n" .align 4  <2 north:~/Examples >gcc example31.s ~cse320/lib/reglib.o <3 north:~/Examples >a.out IU REGISTERS y: 00000000 psr: fe401000 icc: 4 (-Z--) r00: 00000000 r08: 00000000 r16: 00010b88 r24: 00000001 r01: ffffffff r09: 00000000 r17: 00010b90 r25: ffbff6d4 r02: 00000000 r10: 00000000 r18: 00010b98 r26: ffbff6dc r03: 00000000 r11: 00000000 r19: 00000000 r27: 00021a40 r04: 00000000 r12: 00000000 r20: 00000000 r28: 00000000 r05: ffffffff r13: 00000000 r21: 00000000 r29: ff1f0140 r06: 00000000 r14: ffbff600 r22: 00000000 r30: ffbff670 r07: ff1f2a00 r15: 00010b40 r23: 00000000 r31: 00010984 FPU REGISTERS fsr: 00000800 fcc: 2 (GT) f00: ffffffff f08: ffffffff f16: 404b8000 f24: 3ff00000 f01: ffffffff f09: ffffffff f17: 00000000 f25: 00000000 f02: ffffffff f10: ffffffff f18: 40260000 f26: 40240000 f03: ffffffff f11: ffffffff f19: 00000000 f27: 00000000 f04: ffffffff f12: ffffffff f20: ffffffff f28: ffffffff f05: ffffffff f13: ffffffff f21: ffffffff f29: ffffffff f06: ffffffff f14: ffffffff f22: ffffffff f30: ffffffff f07: ffffffff f15: ffffffff f23: ffffffff f31: ffffffff DP REGISTERS fsr: 00000800 fcc: 2 (GT) f00: ffffffffffffffff (-NaN) f02: ffffffffffffffff (-NaN) f04: ffffffffffffffff (-NaN) f06: ffffffffffffffff (-NaN) f08: ffffffffffffffff (-NaN) f10: ffffffffffffffff (-NaN) f12: ffffffffffffffff (-NaN) f14: ffffffffffffffff (-NaN) f16: 404b800000000000 (+5.500000000000000e+01) f18: 4026000000000000 (+1.100000000000000e+01) f20: ffffffffffffffff (-NaN) f22: ffffffffffffffff (-NaN) f24: 3ff0000000000000 (+1.000000000000000e+00) f26: 4024000000000000 (+1.000000000000000e+01) f28: ffffffffffffffff (-NaN) f30: ffffffffffffffff (-NaN) Total: 55.00 FPU REGISTERS fsr: 00000800 fcc: 2 (GT) f00: 00000000 f08: 00000000 f16: 00000000 f24: 00000000 f01: 00000000 f09: ffffffff f17: 00000000 f25: 00000000 f02: 40b57c00 f10: 0000157c f18: 00000000 f26: 00000000 f03: 00000000 f11: ffffffff f19: 00000000 f27: 00000000 f04: 00000000 f12: 00000000 f20: 00000000 f28: 00000000 f05: 00000000 f13: ffffffff f21: 00000000 f29: 00000000 f06: 00000000 f14: 00000000 f22: 00000000 f30: 00000000 f07: ffffffff f15: ffffffff f23: 00000000 f31: 00000000