Patents Awarded

Nano-Scale, Hook-and-Loop Fastener

Micro-fastening system and method of manufacture
by David Tomanek, Richard Enbody, and Young-Kyun Kwon,
United States Patent No. 7,181,811
February 27, 2007.

This system provides a novel way to strongly bond materials. It is a hook-and-loop, fastening system using nanotubes to form the hooks and loops--similar to macro-scale fasteners in common use on clothing. Since carbon nanotubes are one of the strongest materials known and since they are stable to thousands of degrees Kelvin, this bonding mechanism will be very strong. Imagine bonding not only the wings of an aircraft, but also the turbine blades. Unlike macro-scale hook-and-loop fasteners, the unyielding nature of nanotubes prevents it from coming apart. Since carbon nanotubes can be made to be either conducting or non-conducting this bonding process can be either. While it can be used for large scale bonding it can also be used for bonding nanoscale devices such as miniature robots small enough to work in blood vessels.

The figure shows two carbon nanotube hooks fastened together. Each green or red sphere is a carbon atom. That's how small one pair of hooks is. Now imagine the billions of hooks you could fit in a square inch. Hence, the strength of the bond.

The photograph is of an actual nano-hook.

An article on properties of this hook-and-loop fastener appears in Physical Review Letters volume 91 issue 16, page 165503, October 1, 2003.

Assignee: Board of Trustees operating Michigan State University (East Lansing, MI)
Filed: February 11, 1999

Nanomemory

Nanocapsules containing charged particles, their uses and methods of forming the same
by David Tomanek, Richard Enbody, Young-Kyun Kwon, and Mark W. Brehob.
United States Patent No. 6,473,351
October 29, 2002
Sold, Fall 2006.

This device is a nanoscale, computer-memory cell providing orders-of-magnitude improvement in RAM density along with picosecond switching speeds. It should also be non-volatile, i.e. it does not require power to preserve its memory.

Patent Abstract
Nanomechanisms are employed in nanomemory elements which, in turn, are employable in nanoscale memory devices. A nanoscale particle is enclosed within a nonocapsule to create a bistable device which is both readable and writable in a variety of ways. A nonamechanism for use in a nanoscale memory element includes a first element in the form of a nanoassembly having a cavity and second element in the form of a nanostructure which is removeably disposed within the cavity. In one embodiment, the nanoassembly is demonstrated as a C-480 capsule and the nanostructure is demonstrated as a charged C-60 fullerene molecule. The nanoscale memory devices combine high switching speed, high packing density and stability with non-volatility of the stored data.

Assignee: Board of Trustees operating Michigan State University (East Lansing, MI)
Filed: August 9, 2001

Patents Pending

Secure Bit

Hardware Buffer-Overflow Prevention
by Richard Enbody and Krerk Piromsopa
U.S. Patent application Serial No. PCT/US2005/039896
filed November 2004

Secure Bit 2 is a Transparent, Hardware solution against Buffer-Overflow attacks on control data (return-address and function-pointer attacks in particular). It is a continuation of our original work on Secure Bit: both are based on an added Secure Bit, but the management of the bit is dramatically different. We refer to the new management scheme as Secure Bit 2. Secure Bit is a concept to provide a hardware bit to protect the integrity of addresses for the purpose of preventing buffer-overflow attacks. SecureBit2 is our second implementation of a protocol to manage the Secure Bit. SecureBit2 is completely transparent to software, and provides 100% backward compatible with legacy code. Unlike several methods that only reduce the probability of a successful attack, SecureBit2 can detect and prevent all address-corrupting buffer-overflow attacks. SecureBit2 is transparent to software, and has little run-time performance penalty (almost none). The goal of SecureBit2 is to provide hardware support to protect against current and future generations of buffer-overflow attacks by protecting the integrity of addresses: addresses passed in buffers between processes are invalid. Robustness and transparency are demonstrated by emulating the hardware, and booting Linux on the emulator, running application software on that Linux, and performing known attacks.

For details see Piromsopa and Enbody, "Secure Bit : Transparent, Hardware Buffer-Overflow Protection," IEEE Transactions on Dependable and Secure Computing, Vol. 3, No. 4, October-December 2006.

Canary Bit

Canary Bit
by Richard Enbody and Krerk Piromsopa
preliminary patent filed October 2006

This patent builds on the secure platform provided by Secure Bit to cover non-control data, i.e. data not covered by Secure Bit. The basic idea is to use Canary Words, but protect them with Secure Bit. Canary Words have been shown to be effective and are in use, but securing them has been complicated and not without vulnerabilities. Secure Bit provides a simple and secure method of protecting Canary Words.

Segmentation Strategy Tools

iS3 Tools: i-Safety Segmentation Strategy Tools
by Richard Enbody, Nora Rifon, and Robert Larose
preliminary patent filed October 2006

This patent covers our technique for segmenting groups of people so we can apply targeted educational curricula, i-safety in particular.